defining a degree of excellence corporate office bel fuse inc. 198 van vorst street, jersey city, nj 07302-4496 tel: 201-432-0463 fax: 201-432-9542 e-mail: belfuse@compuserve.com internet: http://www.belfuse.com specifications subject to change without notice. far east office bel fuse ltd. 8f/8 luk hop street san po kong kowloon, hong kong tel: 852-2328-5515 fax: 852-2352-3706 european office bel fuse europe ltd. preston technology management centre marsh lane, preston pr1 8ud lancashire, u.k. tel: 44-1772-556601 fax: 44-1772-888366 cat 36 - r0 22 other delays and tolerances available consult sales 5 tap leading edge control low voltage delay modules transfer molded for better reliability compatible with ttl & cmos circuits terminals: electro-tin plate phosphor bronze performance warranty is limited to specified parameters listed smd - tape & reel available: 24mm wide x 12mm pitch, 750 pieces per 13" reel test conditions @ 25 o c electrical characteristics drive capabilities nh logic 1 fanout - 10 lsttl loads max. nl logic 0 fanout - 10 lsttl loads max. 3.0 volts 3.0 ns (10%-90%) 1.2 x total delay 4 x pulse width 25 ma typical 3.3 volts max. 3.6 0.8 -20 20 -20 0.1 -0.5 1 -1 10 30 70 o 50 units v v v ma ma ma v v v ua ua ma ma c % % min. 3.0 2.4 2.9 0 o 40 100 + (25000/td) ppm/ o c 300 o c time in minutes for 90 seconds max > 185 o c 225 o c max temp. infra red 0 200 o c 100 o c temp. 8 6 4 2 recommended temperature profile notes vcc vih vil iik ioh iol voh vol vik iih iil icch iccl ta pw d tc supply voltage logic 1 input voltage logic 0 input voltage input clamp current logic 1 output current logic 0 output current logic 1 output voltage logic 0 output voltage input clamp voltage logic 1 input current logic 0 input current logic 1 supply current logic 0 supply current operating free air temperature min. input pulse width of total delay maximum duty cycle temp. coeff. of total delay (td) ein trin pw pp iccl vcc pulse voltage rise time pulse width pulse period supply current supply voltage part numbers input to taps + 2 ns or 5 % , whichever is greater tap to tap + 2 ns or 7%, whichever is greater delays measured @ 50% levels on leading edge only with no loads on taps rise and fall times measured from 10% to 90% levels tolerances 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns 3 ns smd thru-hole total delay delay per tap 25 ns 30 ns 35 ns 40 ns 45 ns 50 ns 60 ns 70 ns 80 ns 90 ns 100 ns 125 ns 150 ns 5 ns 6 ns 7 ns 8 ns 9 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns 25 ns 30 ns s473-0025-02 s473-0030-02 s473-0035-02 s473-0040-02 s473-0045-02 s473-0050-02 s473-0060-02 s473-0070-02 s473-0080-02 s473-0090-02 s473-0100-02 s473-0125-02 s473-0150-02 a473-0025-02 a473-0030-02 a473-0035-02 a473-0040-02 a473-0045-02 a473-0050-02 a473-0060-02 a473-0070-02 a473-0080-02 a473-0090-02 a473-0100-02 a473-0125-02 A473-0150-02 * 4 o .285 max ( p/n ) .10 typ bel ( dc ) in 1 .030 .015 .004 .012 .008 .285 max .10 typ .018 .22 max .350 bel ( dc ) ( p/n ) .375 .300 .50 max vcc 8 gnd 4 7 2 6 3 5 .300 .50 max .325 .20 max .015 min .045 .018 .23 max 100 o 90 o .012 .008 .12 min coplanarity + .002 rise time
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